The present invention is concerned with testing wafers on which electronic circuits are formed, and is more particularly concerned with testing electronic circuits used in optical communications systems.
It is well known to apply tests to electronic circuits formed on semiconductor wafers. A purpose of such testing is to determine whether the electronic circuits had been properly manufactured to perform their desired functions.
Some types of integrated circuits (ICs) are manufactured for use in optical communications systems.
FIG. 1 is a schematic illustration of a conventional arrangement in which an electronic IC 10 is utilized in an optical communications system. The electronic IC 10 is coupled between a photo detector 12 which provides an electrical input signal for the electronic IC 10, and a light source 14 which is driven by an electrical signal from the electronic IC 10. The electronic IC 10 has receiver functions that respond to the electrical input signal from the photo detector 12, and transmitter functions that produce the electrical signal which drives the light source 14. The photo detector 12 may be a PIN diode or an avalanch photo detector (APD). The light source 14 may be an LED (light emitting diode) or a laser.
Typically electronic ICs manufactured for optical communications are not produced on the same wafer with optical elements because different manufacturing processes are required for the electronic circuits and the optical elements. Instead, after testing, each die containing an electronic IC is cut from its wafer and then packaged with associated optical elements.
According to conventional practices, during testing of the electronic IC die on a wafer, the photo detector with which the IC is to be packaged is simulated by using a current source in parallel with a capacitor. A resistor is conventionally used to simulate the light source that the electronic IC is intended to drive.
However, there are significant differences in performance between the actual optical elements and the circuit elements conventionally used to simulate them during wafer testing. As a result, tests that would be desirable to perform on a wafer cannot be carried out. For example, the frequency performance of a PIN diode is dependent on the incident optical power. When the incident optical power is at a high level, the bandwidth of the PIN diode is reduced. Conventional electronic circuits used in optical communications systems include a function to compensate for the drop in bandwidth at high optical power. This function is very important to insure that the optical communications system operates in accordance with specifications in a high optical power environment, and consequently, the function should be tested at the wafer level. However, this function is not tested on the wafer because the mechanism of the bandwidth reduction of the PIN diode at high incident optical power is quite complex and cannot be simulated by a simple change of parallel capacitance.
The limitations on wafer testing of electronic ICs for optical communications systems, due to the inexact simulation of optical elements, may lead to the following problems. First, some bad dies may be passed through wafer testing, only to be found in package level tests. The cost of inking out a bad die is relatively low, on the order of several tens of cents, but after a die is packaged and found to be bad, the cost is on the order of several dollars at least. Consequently passing a bad die through wafer testing may cause a ten-fold increase in expense due to the original manufacturing failure relative to the bad die.
Secondly, when package level testing indicates a fault in a package, it can be difficult to determine whether the fault is due to the electronics IC (i.e., a bad die) or problems with the optical components. Consequently, it may be necessary to undertake an expensive debugging procedure which entails a significant amount of engineering time to determine the cause of the failure. It accordingly would be very desirable to weed out all bad dies at the wafer test level. However, this is not feasible with conventional wafer testing procedures and wafer testing apparatus used in connection with electronic ICs for optical communications systems.
It accordingly would be desirable to improve the capabilities of wafer test equipment used in regard to electronic ICs for optical communications systems with respect to representation of optical components.
It would also be desirable that the test apparatus components which represent optics be capable providing a very wide range of signal power. This is because, especially in the case of xe2x80x9copen spacexe2x80x9d optical communications devices (i.e., devices in which no optical wave guide is employed), the incident optical power to a photo detector may vary over up to 6 orders of magnitude as the communication distance varies.
It would also be desirable that the test apparatus not provide false indications of die failures due to aging of components of the test apparatus.
According to a first aspect of the invention, a method of testing an electronic device on a wafer is provided. The method includes generating an optical test signal, providing the optical test signal to a first photo detector, and supplying an electrical output of the first photo detector to the electronic device on the wafer.
According to a second aspect of the invention, a method of testing an electronic device on a wafer includes driving a light source with an electrical output from the electronic device on the wafer, supplying an optical output of the light source to a second photo detector, and examining an electrical signal output from the second photo detector.
The optical test signal may be provided to the first photo detector via a first variable optical attenuator and the optical output of the light source may be supplied to the second photo detector via a second variable optical attenuator.
According to a third aspect of the invention, an apparatus for testing an electronic device on a wafer includes the following elements:
a first light source for generating an optical test signal in accordance with a test control signal;
(b) a first variable optical attenuator coupled to the first light source for receiving and attenuating the optical test signal to produce an attenuated optical test signal;
(c) a first photo detector coupled to the first variable optical attenuator for receiving the attenuated optical test signal and converting the attenuated optical test signal into an electrical test signal;
(d) first probes for selectively coupling the electrical test signal to the electronic device on the wafer;
(e) a second light source;
(f) a second probe for receiving an electrical output from the electronic device on the wafer and selectively coupling the electrical output from the electronic device on the wafer to drive the second light source to output an optical output signal;
(g) a second variable optical attenuator coupled to the second light source for receiving and attenuating the optical output signal to produce an attenuated optical output signal;
(h) a second photo detector coupled to the second optical attenuator for receiving the attenuated optical output signal and converting the attenuated optical output signal into an electrical detection signal; and
(i) a first monitoring circuit coupled to the second photo detector for receiving and monitoring the electrical detection signal.
With the methods and apparatus of the present invention, a more complete set of wafer-level tests may be performed on electronic circuits to be used in optical communications systems. Consequently defects in the electronic circuitry can be reliably detected prior to packaging, so that costs of manufacturing failures and debugging time are reduced.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.